In the prior art, in order to improve the mobility of thin film transistors, a double-gate structure, i.e., a structure with an upper gate electrode and a lower gate electrode, can be used to induce double channels at a semiconductor layer to enlarge a conducting pathway.
FIG. 1 is a schematic structure diagram of a thin film transistor having a double-gate structure in the prior art As shown in FIG. 1, an upper gate electrode 1 of the thin film transistor is overlapped on a source electrode 2 and a drain electrode 3. When the voltages of the upper gate electrode 1 and the lower gate electrode 4 both reach a turn-on voltage (the turn-on voltage is a threshold voltage, and when a voltage of a gate electrode is greater than the turn-on voltage, a conducting channel can be formed in the semiconductor layer by induction), an upper conducting channel and a lower conducting channel which are parallel to each other can be formed in the semiconductor layer 5 by induction. Since the upper gate electrode 1 is overlapped on the source electrode 2 and the drain electrode 3, that is, in a plane parallel with the conducting channel in the semiconductor layer 5, an orthographic projection of the upper gate electrode 1 is partially overlapped with an orthographic projection of the source electrode 2 and an orthographic projection of the drain electrode 3 respectively, the drain electrode 3 can be conducted with the source electrode 2 separately by the upper conducting channel. In addition, the drain electrode 3 can also be conducted with the source electrode 2 separately by the lower conducting channel. However, for thin film transistors with such a double-gate structure, it is difficult to ensure the improvement of mobility by simultaneous conduction of the upper conducting channel and the lower conducting channel.
Because of process technologies, it is difficult to match parameters such as capacitance of an upper insulating layer 6 below the upper gate electrode 1 and a lower insulating layer 7 above the lower gate electrode. This will result in different turn-on voltages of the upper conducting channel and the lower conducting channel respectively formed in the upper gate electrode 1 and the lower gate electrode 4. Thus, it is difficult to achieve simultaneous conduction of the upper conducting channel and the lower conducting channel in the thin film transistor structure in the prior art.